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lt3751 1 3751fc typical a pplica t ion fea t ures a pplica t ions descrip t ion high voltage capacitor charger controller with regulation the lt ? 3751 is a high input voltage capable flyback con- troller designed to rapidly charge a large capacitor to a user-adjustable high target voltage set by the transformer turns ratio and three external resistors. optionally, a feed- back pin can be used to provide a low noise high voltage regulated output. the lt3751 has an integrated rail-to-rail mosfet gate driver that allows for efficient operation down to 4.75v. a low 106 mv differential current sense threshold voltage accurately limits the peak switch current. added pro- tection is provided via user-selectable overvoltage and undervoltage lockouts for both v cc and v trans . a typical application can charge a 1000 f capacitor to 500 v in less than one second. the charge pin is used to initiate a new charge cycle and provides on/off control. the done pin indicates when the capacitor has reached its programmed value and the part has stopped charging. the fault pin indicates when the lt3751 has shut down due to either v cc or v trans voltage exceeding the user- programmed supply tolerances. n charges any size capacitor n low noise output in voltage regulation mode n stable operation under a no-load condition n integrated 2 a mosfet gate driver with rail-to-rail operation for v cc 8v n selectable 5.6v or 10.5v internal gate drive v oltage clamp n user-selectable over/undervoltage detect n easily adjustable output voltage n primary or secondary side output voltage sense n wide input v cc voltage range (5v to 24v) n available in 20-pin qfn 4mm 5mm and 20-lead tssop packages n high voltage regulated supply n high voltage capacitor charger n professional photoflash systems n emergency strobe n security/inventory control systems n detonators charge clamp v cc done fault uvlo1 ovlo1 uvlo2 ovlo2 rdcm rv out hvgate lvgate csp csn fb rv trans t1 1:10 d1 500v 0 to 150ma v trans 24v v cc 10f 2 3751 ta01a lt3751 danger high voltage! operation by high voltage trained personnel only gnd rbg 40.2k off on 330f 2 v cc 24v 10f ? ? 18.2k 40.2k 6m + + 100f 715k 1.74k 10nf 732 v trans v cc to micro 0.47f 374k 475k 475k 374k load current (ma) 0 output voltage (v) efficiency (%) 500 498 494 496 492 490 90 84 72 78 66 60 100 50 3751 ta01b 150 output voltage efficiency load regulation and efficiency l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6518733 and 6636021.
lt3751 2 3751fc a bsolu t e maxi m u m r a t ings v cc , charge , clamp .............................................. 24 v d one , fa u lt ............................................................ 24 v lv gate ( note 8) ....................................................... 24 v v cc C lvgate ............................................................. 8 v hvgate ................................................................ no te 9 rbg , csp , csn ........................................................... 2 v fb .............................................................................. 5 v current into done pin ........................................... 1 ma c urrent into fa u lt pin ........................................... 1 ma cu rrent into rv trans pin ....................................... 1 ma (note 1) o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt3751efe#pbf lt3751efe#trpbf lt3751fe 20-lead plastic tssop C40c to 125c lt3751ife#pbf lt3751ife#trpbf lt3751fe 20-lead plastic tssop C40c to 125c lt3751eufd#pbf lt3751eufd#trpbf 3751 20-pin (4mm 5mm) plastic qfn C40c to 125c lt3751iufd#pbf lt3751iufd#trpbf 3751 20-pin (4mm 5mm) plastic qfn C40c to 125c lead based finish tape and reel part marking* package description temperature range lt3751efe lt3751efe#tr lt3751fe 20-lead plastic tssop C40c to 125c lt3751ife lt3751ife#tr lt3751fe 20-lead plastic tssop C40c to 125c lt3751eufd lt3751eufd#tr 3751 20-pin (4mm 5mm) plastic qfn C40c to 125c lt3751iufd lt3751iufd#tr 3751 20-pin (4mm 5mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ current into rv out pin ........................................ 10 ma c urrent into rdcm pin......................................... 10 ma current into uvlo1 pin .......................................... 1 ma c urrent into uvlo 2 pin .......................................... 1 ma current into ovlo1 pin .......................................... 1 ma c urrent into ovlo 2 pin .......................................... 1 ma m aximum junction temperature .......................... 12 5 c operating temperature range ( note 2) .. C 40 c to 125 c storage temperature range .................. C 6 5 c to 125 c fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 rv trans uvlo1 ovlo1 uvlo2 ovlo2 fault done charge clamp fb rdcm nc rv out nc rbg hvgate lvgate v cc csp csn 21 t jmax = 125c, ja = 38c/w exposed pad (pin 21) is gnd, must be soldered to pcb 20 19 18 17 7 8 top view ufd package 20-pin (4mm 5mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 ovlo1 uvlo2 ovlo2 fault done charge rv out nc rbg hvgate lvgate v cc uvlo1 rv trans nc rdcm clamp fb csn csp 21 t jmax = 125c, ja = 43c/w exposed pad (pin 21) is gnd, must be tied to pcb p in c on f igura t ion
lt3751 3 3751fc e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are t a = 25c. v cc = charge = 5v, clamp = 0v, unless otherwise noted. individual 25k resistors tied from 5v v trans supply to rv trans , rv out , rdcm, unless otherwise noted. (note 2) parameter conditions min typ max units v cc voltage l 4.75 24 v rv trans voltage (note 3) l 4.75 65 v v cc quiescent current not switching, charge = 5v not switching, charge = 0.3v 5.5 0 8 1 ma a rv trans , r dcm quiescent current (note 4) not switching, charge = 5v not switching, charge = 0.3v l 35 40 0 45 1 a a rv out quiescent current (note 4) not switching, charge = 5v not switching, charge = 0.3v l 42 47 0 52 1 a a uvlo1, uvlo2, ovlo1, ovlo2 clamp voltage measured at 1ma into pin, charge = 0v 55 v rv trans , rv out , r dcm clamp voltage measured at 1ma into pin, charge = 0v 60 v charge pin current charge = 24v charge = 5v charge = 0v 425 60 1 a a a charge minimum enable voltage l 1.5 v charge maximum disable voltage i vcc 1a l 0.3 v minimum charge pin low time 20 s one-shot clock period l 32 38 44 s v out comparator trip voltage measured at rbg pin l 0.955 0.98 1.005 v v out comparator overdrive 2s pulse width, rv trans , rv out = 25k? r bg = 0.83k? 20 40 mv dcm comparator trip voltage measured as v drain C v trans , r dcm = 25k, v cc = 4.75v (note 5) 350 600 900 mv current limit comparator trip voltage fb pin = 0v fb pin = 1.3v l l 100 7 106 11 112 15 mv mv fb pin bias current current sour ced from fb pin, measured at fb pin voltage 64 300 na fb pin voltage (note 6) l 1.19 1.22 1.25 v fb pin charge mode threshold 1.12 1.16 1.2 v fb pin charge mode hysteresis (note 7) 55 mv fb pin overvoltage mode threshold 1.29 1.34 1.38 v fb pin overvoltage hysteresis 60 mv done output signal high 100k to 5v 5 v done output signal low 100k to 5v 40 200 mv done leakage current done = 5v 5 200 na fault output signal high 100k to 5v 5 v fault output signal low 100k to 5v 40 200 mv fault leakage current fault = 5v 5 200 na uvlo1 pin current uvlo1 pin voltage = 1.24v l 48.5 50 51.5 a uvlo2 pin current uvlo2 pin voltage = 1.24v l 48.5 50 51.5 a ovlo1 pin current ovlo1 pin voltage = 1.24v l 48.5 50 51.5 a ovlo2 pin current ovlo2 pin voltage = 1.24v l 48.5 50 51.5 a
lt3751 4 3751fc e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are t a = 25c. v cc = charge = 5v, clamp = 0v, unless otherwise noted. individual 25k resistors tied from 5v v trans supply to rv trans , rv out , rdcm, unless otherwise noted. (note 2) parameter conditions min typ max units uvlo1 threshold measured from pin to gnd l 1.195 1.225 1.255 v uvlo2 threshold measured from pin to gnd l 1.195 1.225 1.255 v ovlo1 threshold measured from pin to gnd l 1.195 1.225 1.255 v ovlo2 threshold measured from pin to gnd l 1.195 1.225 1.255 v gate minimum high time 0.7 s gate peak pull-up current v cc = 5v, lvgate active v cc = 12v, lvgate inactive 2.0 1.5 a a gate peak pull-down current v cc = 5v, lvgate active v cc = 12v, lvgate inactive 1.2 1.5 a a gate rise time 10% 90%, c gate = 3.3nf (note 8) v cc = 5v, lvgate active v cc = 12v, lvgate inactive 40 55 ns ns gate fall time 90% 10%, c gate = 3.3nf (note 8) v cc = 5v, lvgate active v cc = 12v, lvgate inactive 30 30 ns ns gate high voltage (note 8): v cc = 5v, lvgate active v cc = 12v, lvgate inactive v cc = 12v, lvgate inactive, clamp pin = 5v v cc = 24v, lvgate inactive 4.98 10 5 10 5 10.5 5.6 10.5 11.5 6.5 11.5 v v v v gate turn-off propagation delay c gate = 3.3nf 25mv overdrive applied to csp pin 180 ns gate voltage overshoot 500 mv clamp pin threshold 1.6 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3751e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design characterization and correlation with statistical process controls. the lt3751i is guaranteed over the full C40c to 125c operating junction temperature range. note 3: a 60v internal clamp is connected to rv trans , rdcm, rv out , uvlo1, uvlo2, ovlo1 and ovlo2. resistors should be used such that the pin currents do not exceed the absolute maximum ratings. note 4: currents will increase as pin voltages are taken higher than the internal clamp voltage. note 5: refer to block diagram for v trans and v drain definitions. note 6: low noise regulation of the output voltage requires a resistive voltage divider from output voltage to fb pin. fb pin should not be grounded in this configuration. refer to the typical application diagram for proper fb pin configuration. note 7: the feedback pin has built-in hysteresis that defines the boundary between charge-only mode and low noise regulation mode. note 8: lv gate should be used in parallel with hvgate when v cc is less than or equal to 8v (lvgate active). when not in use, lvgate should be tied to v cc (lvgate inactive). note 9: do not apply a positive or negative voltage or current source to hvgate, otherwise permanent damage may occur.
lt3751 5 3751fc typical p er f or m ance c harac t eris t ics v cc pin current v trans supply current charge pin current charge pin minimum enable voltage charge pin maximum disable voltage done, fault pin voltage low v out comparator trip voltage uvlo1 trip voltage uvlo1 trip current pin voltage (v) 0 pin current (ma) 7 6 4 2 5 3 1 0 16 8 20 3751 g01 24 12 4 ?40c 25c 125c pin voltage (v) 0 i vtrans current (a) 150 145 135 120 125 140 130 115 110 40 20 50 3751 g02 60 30 10 ?40c 25c 125c rv trans , rv out , r dcm = 25k v cc , charge = 5v i vtrans = i rvtrans + i rvout + i rdcm pin voltage (v) 0 current (a) 450 400 300 150 200 350 250 100 50 0 16 8 20 3751 g03 24 12 4 ?40c 25c 125c ?40 charge pin voltage (v) 1.3 1.2 1.0 0.7 0.8 1.1 0.9 0.6 40 60 0 80 100 3751 g04 120 20 temperature (c) ?20 v cc = 5v v cc = 12v v cc = 24v ?40 charge pin voltage (v) 1.2 1.1 0.9 0.6 0.7 1.0 0.8 0.5 40 60 0 80 100 3751 g05 120 20 temperature (c) ?20 v cc = 5v v cc = 12v v cc = 24v ?40 pin low voltage (mv) 400 350 200 250 50 100 300 150 0 40 60 0 80 100 3751 g06 120 20 temperature (c) ?20 1ma sink 100a sink 10a sink ?40 v drain ? v trans voltage (v) 30.8 30.4 29.2 29.6 30.0 28.8 28.4 40 60 0 80 100 3751 g07 120 20 temperature (c) ?20 rv trans , rv out = 25.5k (r tol = 1%) r bg = 833 v trans = 5v v trans = 12v v trans = 24v v trans = 48v v trans = 72v ?40 uvlo1 pin voltage (v) 1.236 1.234 1.228 1.230 1.232 1.226 1.224 40 60 0 80 100 3751 g08 120 20 temperature (c) ?20 v cc = 5v v cc = 12v v cc = 24v ?40 uvlo1 pin current (a) 50.5 50.4 49.9 50.2 50.1 50.0 50.3 49.8 49.7 40 60 0 80 100 3751 g09 120 20 temperature (c) ?20 v cc = 5v v cc = 12v v cc = 24v
lt3751 6 3751fc typical p er f or m ance c harac t eris t ics current comparator trip voltage (charge mode) current comparator minimum trip voltage (regulation mode) fb pin regulation mode threshold fb pin regulation mode hysteresis fb pin overvoltage mode threshold voltage fb pin overvoltage mode hysteresis ?40 v th voltage (mv) 109.0 108.5 107.5 108.0 107.0 40 60 0 80 100 3751 g10 120 20 temperature (c) ?20 v cc = 5v v cc = 12v v cc = 24v v th = v csp ? v csn ?40 v th voltage (mv) 13.0 12.4 12.6 12.8 12.2 12.0 11.4 11.6 11.2 11.8 11.0 40 60 0 80 100 3751 g11 120 20 temperature (c) ?20 v cc = 5v v cc = 12v v cc = 24v v th = v csp ? v csn fb = 1.3v ?40 fb pin voltage (v) 1.168 1.164 1.160 1.156 1.152 40 60 0 80 100 3751 g14 120 20 temperature (c) ?20 v cc = 5v v cc = 12v v cc = 24v ?40 hysteresis (mv) 60 58 56 54 52 50 40 60 0 80 100 3751 g15 120 20 temperature (c) ?20 v cc = 5v v cc = 12v v cc = 24v ?40 fb pin voltage (v) 1.356 1.354 1.352 1.350 1.348 1.346 1.344 40 60 0 80 100 3751 g16 120 20 temperature (c) ?20 v cc = 5v v cc = 12v v cc = 24v ?40 hysteresis (mv) 61.0 60.6 60.2 59.8 59.4 59.0 40 60 0 80 100 3751 g17 120 20 temperature (c) ?20 v cc = 5v v cc = 12v v cc = 24v clamp pin threshold ?40 clamp pin voltage (v) 1.9 1.8 1.7 1.6 1.5 1.4 40 0 80 3751 g18 120 temperature (c) v cc = 12v v cc = 24v fb pin voltage fb pin bias current ?40 fb pin voltage (v) 1.223 1.222 1.220 1.221 1.219 40 60 0 80 100 3751 g12 120 20 temperature (c) ?20 v cc = 5v v cc = 12v v cc = 24v ?40 sourced pin current (na) 100 90 80 70 60 50 40 40 60 0 80 100 3751 g13 120 20 temperature (c) ?20 measured at fb pin voltage v cc = 12v
lt3751 7 3751fc t ypical per f or m ance charac t eris t ics rv trans (pin 1/pin 19): transformer supply sense pin. connect a resistor between the rv trans pin and the v trans supply. refer to table 2 for proper sizing of the rv trans resistor. the minimum operation voltage for v trans is 4.75v. uvlo1 (pin 2/pin 20): v trans undervoltage lockout pin. senses when v trans drops below: v uvlo1 = 1.225 + 50 a ? r uvlo1 and trips the fault latch low, disabling switching. after v trans rises above v uvlo1 , toggling the charge pin reactivates switching. ovlo1 (pin 3/pin 1): v trans overvoltage lockout pin. senses when v trans rises above: v ovlo1 = 1.225 + 50 a ? r ovlo1 and trips the fault latch low, disabling switching. after v trans drops below v ovlo1 , toggling the charge pin reactivates switching. uvlo 2 (pin 4/pin 2): v cc undervoltage lockout pin. senses when v cc drops below: v uvlo2 = 1.225 + 50 a ? r uvlo2 and trips the fault latch low, disabling switching. after v cc rises above v uvlo2 , toggling the charge pin reac- tivates switching. ovlo2 (pin 5/pin 3): v cc overvoltage lockout pin. senses when v cc rises above: v ovlo2 = 1.225 + 50 a ? r ovlo2 and trips the fault latch low, disabling switching. after v cc drops below v ovlo2 , toggling the charge pin reac- tivates switching. fault (pin 6/pin 4): open collector indication pin. when either v trans or v cc exceeds the user-selected voltage range, or an internal uvlo condition occurs, a transistor turns on. the part will stop switching. this pin needs a proper pull-up resistor or current source. hvgate pin clamp voltage hvgate pin clamp voltage ?40 hvgate pin voltage (v) 11.0 10.9 10.8 10.7 10.5 10.6 10.4 40 60 0 80 100 3751 g19 120 20 temperature (c) ?20 v cc = 24v clamp = 0v ?40 hvgate pin voltage (v) 5.70 5.65 5.60 5.55 5.50 40 60 0 80 100 3751 g20 120 20 temperature (c) ?20 v cc = 12v clamp = 12v p in func t ions dcm trip voltage (v drain C v trans ), rv trans = rdcm = 25k ?40 dcm trip voltage (v) 0.64 0.62 0.60 0.58 0.56 0.54 40 0 80 3751 g21 120 temperature (c) v trans = 5v v trans = 12v v trans = 24v v trans = 48v (tssop/qfn)
lt3751 8 3751fc p in func t ions done (pin 7/ pin 5): open collector indication pin. when the target output voltage ( charge mode) is reached or the fault pin goes low, a transistor turns on. this pin needs a proper pull-up resistor or current source. charge (pin 8/pin 6): charge pin. initiates a new charge cycle ( charge mode) or enables the part ( regulation mode) when driven higher than 1.5 v. bring this pin below 0.3v to discontinue charging and put the part into shutdown. turn-on ramp rates should be between 10 ns to 10ms. charge pin should not be directly ramped with v cc or lt3751 may not properly initialize. clamp (pin 9/pin 7): internal clamp voltage selection pin. tie this pin to v cc to activate the internal 5.6 v gate driver clamp. tie this pin to ground to activate the internal 10.5v gate driver clamp. fb (pin 10/pin 8): feedback regulation pin. use this pin to achieve low noise voltage regulation. fb is internally regulated to 1.22 v when a resistive divider is tied from this pin to the output. fb pin should not float. tie fb pin to either a resistor divider or ground. csn (pin 11/pin 9): negative current sense pin. senses external nmos source current. connect to local r sense ground connection for proper kelvin sensing. the current limit is set by 106mv/r sense . csp (pin 12/pin 10): positive current sense pin. senses nmos source current. connect the nmos source terminal and the current sense resistor to this pin. the current limit is fixed at 106mv/r sense in charge mode. the cur- rent limit can be reduced to a minimum 11mv/r sense in regulation mode. v cc ( pin 13/pin 11): input supply pin. must be locally by- passed with high grade ( x5r or better) ceramic capacitor. the minimum operating voltage for v cc is 4.75v. lvgate (pin 14/pin 12): low voltage gate pin. connect the nmos gate terminal to this pin when operating v cc below 8 v. the internal gate driver will drive the voltage to the v cc rail. when operating v cc higher than 8 v, tie this pin directly to v cc . hvgate (pin 15/pin 13): high voltage gate pin. connect nmos gate terminal to this pin for all v cc operating volt- ages. internal gate driver will drive the voltage to within v cc C 2v during each switch cycle. rbg ( pin 16/pin 14): bias generation pin. generates a bias current set by 0.98 v/r bg . select r bg to achieve desired resistance for r dcm , rv out , and rv trans . nc (pins 17, 19/pins 15, 18): no connection. rv out (pin 18/pin 16): output voltage sense pin. devel- ops a current proportional to the output capacitor volt- age. connect a resistor between this pin and the drain of nmos such that: v out = 0.98 ? n ? rv out r bg ? ? ? ? ? ? ? v diode when rv out is set equal to rv trans , otherwise: v out = n ? 0.98 ? rv out r bg + v trans rv out rv trans ? 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? v diode where v diode = forward voltage drop of diode d 1 ( refer to the block diagram). rdcm (pin 20/pin 17): discontinuous mode sense pin. senses when the external nmos drain is equal to 20a ? r dcm + v trans and initiates the next switch cycle. place a resistor equal to 0.45 times the resistor on the rv trans pin between this pin and v drain . gnd ( pin 21/pin 21): ground. tie directly to local ground plane.
lt3751 9 3751fc b lock diagra m + fb csn csp lvgate hvgate clamp 3751 bd start-up one-shot charge v cc otlo master latch s q r q enable gate driver onoff done fault 100k 10f 100k s q r q v cc 12v internal uvlo 3.8v v cc ? + + ? ? + + ? ? + 55v 55v uvlo1 ovlo1 uvlo2 ovlo2 55v 55v r uvlo1 191k r uvlo2 191k r ovlo1 240k r ovlo2 240k 1.22v reference uvlo/ovlo comparators r bg 1.33k gnd rbg to v out comparator v out comparator ? + dcm one-shot ? + dcm comparator 26khz one-shot clock s r q q counter 26khz one-shot clock switch latch 0.98v reference diff. amp comparator with internal 60v clamps 1.22v reference gate drive circuitry 60v rv out 60v rdcm ? + ? + ? + reset clk count + ? + ? timing and peak current control ? + 26khz one-shot clock mode control die temp 160oc 1.22v reference ? ? 60v rv out 40.2k r dcm 18.2k m1 v cc r sense 12m error amp a1 11mv to 106mv modulation 106mv 162mv rv trans rv trans 40.2k 10f 47f 2 d1 t1 1:10 primary secondary + v out 450v c out r fbh 3.65m r fbl 10k v trans 12v v trans v cc to charge one-shot v cc v cc v drain 10nf auxiliary main fault latch
lt3751 10 3751fc o pera t ion the lt3751 can be used as either a fast, efficient high voltage capacitor charger controller or as a high voltage, low noise voltage regulator. the fb pin voltage determines one of the three primary modes: charge mode, low noise regulation, or no- load operation ( see figure 1). figure 1. fb pin modes c harge m ode when the fb pin voltage is below 1.16 v, the lt3751 acts as a rapid capacitor charger. the charging operation has four basic states for charge mode steady-state operation (see figure 2). 1. start-up the first switching cycle is initiated approximately 2 s after the charge pin is raised high. during this phase, the start-up one-shot enables the master latch turning on the external nmos and beginning the first switching cycle. after start-up, the master latch will remain in the switching-enable state until the target output voltage is reached or a fault condition occurs. the lt3751 utilizes circuitry to protect against transformer primary current entering a runaway condition and remains in start-up mode until the dcm comparator has enough headroom. refer to the start-up protection section for more detail. 2. primary-side charging when the nmos switch latch is set, and depending on the use of lvgate, the gate driver rapidly charges the gate pin to v cc C 2 v in high voltage applications or directly to v cc in low voltage applications ( refer to the application fb pin voltage 3751 f01 no-load operation regulation charge mode 1.34v 1.16v 0.0v figure 2. idealized charging waveforms v trans ? v ds(on) l pri v trans ? v ds(on) ?n (v trans ? v ds(on) ) v out + v diode v out + v diode l sec i pk i pk n ?(v out + v diode ) n i lpri i lsec v pri v sec v drain v out + v diode n v trans + v trans v ds(on) 3751 f02 v ds(on) 1. primary-side charging 2. secondary energy transfer and output detection 3. discontinuous mode detection
lt3751 11 3751fc information section for proper use of lvgate). with the gate driver output high, the external nmos turns on, forcing v trans C v ds(on) across the primary winding. consequently, current in the primary coil rises linearly at a rate (v trans C v ds(on) )/l pri . the input voltage is mir- rored on the secondary winding C n ? ( v trans C v ds(on) ) which reverse-biases the diode and prevents current flow in the secondary winding. thus, energy is stored in the core of the transformer. 3. secondary energy transfer when current limit is reached, the current limit comparator resets the nmos switch latch and the device enters the third phase of operation, secondary energy transfer. the energy stored in the transformer core forward-biases the diode and current flows into the output capacitor. during this time, the output voltage ( neglecting the diode drop) is reflected back to the primary coil. if the target output voltage is reached, the v out comparator resets the master latch and the done pin goes low. otherwise, the device enters the next phase of operation. 4. discontinuous mode detection during secondary energy transfer to the output capaci- tor, (v out + v diode )/n will appear across the primary winding. a transformer with no energy cannot support a dc voltage, so the voltage across the primary will decay to zero. in other words, the drain of the nmos will ring down from v trans + (v out + v diode )/n to v trans . when the drain voltage falls to v trans + 20a ? r dcm , the dcm opera t ion figure 3. start-up protection circuitry figure 4. dcm comparator thresholds comparator sets the nmos switch latch and a new switch cycle begins. steps 2-4 continue until the target output voltage is reached. start-up protection the lt3751 at start-up, when the output voltage is very low ( or shorted), usually does not have enough v drain node voltage to trip the dcm comparator. the part in start- up mode uses the internal 26 khz clock and an auxiliary current comparator. figure 3 shows a simplified block diagram of the start-up circuitry. from auxiliary current comparator 3751 f03 from clk from gate driver on from dcm comparator reset increment counter 2 reset increment counter 1 ? + switch latch start-up (dcm threshold = v th1 ) below v th2 (wait for time-out) v drain 3751 f04 v out dcm 1-shot v th1 v th2 v ! boundary-mode (dcm threshold = v th2 ) t toggling the charge pin always generates a start-up one- shot to turn on the external switch, initiating the charg- ing process. after the start-up one-shot, the lt3751 waits for either the dcm comparator to generate a one-shot or the output of the start-up protection circuitry going high, which ever comes first. if the switch drain node, v drain , is below the dcm comparator threshold ( see entering normal boundary mode), the dcm comparator will never fire and the start-up circuitry is dominant.
lt3751 12 3751fc o pera t ion at very low output voltages, the boundary -mode switching cycle period increases significantly such that the energy stored in the transformer core is not depleted before the next clock cycle. in this situation, the clock may initiate another switching cycle before the secondary winding current reaches zero and cause the lt3751 to enter continuous-mode conduction. normally, this is not a problem; however, if the secondary energy transfer time is much longer than the clk period, significant primary current overshoot can occur. this is due to the non-zero starting point of the primary current when the switch turns on and the finite speed of the current comparator. the lt3751 startup circuitry adds an auxiliary current comparator with a trip level 50% higher than the nominal trip level. every time the auxiliary current comparator trips, the required clock count between switching cycles is incremented by one. this allows more time for secondary energy transfer. counter 1 in figure 3 is set to its maximum count when the first dcm comparator one-shot is generated . if no dcm one- shot is initiated in normal boundary - mode operation during a maximum count of approximately 500s, the lt3751 re-enters start-up mode and the count is returned to zero. note that counter 1 is initialized to zero at start-up. thus, the output of the startup circuitry will go high after one clock cycle. counter 2 is reset when the gate driver goes high. this repeats until either the auxiliary current comparator increments the required clock count or until v drain is high enough to sustain normal operation described in steps 2 through 4 in the previous section. entering normal boundary mode the lt3751 has two dcm comparator thresholds that are dependent on what mode the part is in, either start- up mode or normal boundary-mode, and the state of the mode latch. for boundary-mode switching, the lt3751 requires the dcm sense voltage ( v drain ) to exceed v trans by the dcm comparator threshold, v drain : v drain = (40a + i offset ) ? r dcm C 40a ? rv trans where i offset is mode dependent. the dcm one-shot signal is negative edge triggered by the switch node, v drain , and indicates that the energy in the secondary winding has depleted. for this to happen, v drain must exceed v trans + v drain prior to its negative edge; oth- erwise, the dcm comparator will not generate a one-shot to initiate the next switching cycle . the part would remain stuck in this state indefinitely; however, the lt3751 uses the start-up protection circuitry to jumpstart switching if the dcm comparator does not generate a one-shot after a maximum time-out of 500s. figure 4 shows a typical v drain node waveform with a test circuit voltage clamp applied to the output. v th1 is the start-up threshold and is set internally by forcing i offset to 40 a. once the first dcm one-shot is initiated, the mode latch is set to boundary-mode. the mode latch then sets the clock count to maximum (500 s) and lowers the dcm comparator threshold to v th2 (i offset = 20a). this provides needed hysteresis between start-up mode and boundary-mode operation. l ow n oise r egula tion low noise voltage regulation can be achieved by adding a resistive divider from the output node to the lt3751 fb pin. at start-up (fb pin below 1.16v), the lt3751 enters the charge mode to rapidly charge the output capacitor. once the fb pin is within the threshold range of 1.16v to 1.34 v, the part enters into low noise regulation. the switching methodology in regulation mimics that used in the capacitor charging mode , but with the addition of peak current and duty cycle control techniques. figure 5 shows the steady state operation for both regulation techniques. figure 6 shows how both techniques are combined to provide stable, low noise operation over a wide load and supply range. during heavy load conditions, the lt3751 sets the peak primary current to its maximum value , 106 mv/r sense and sets the maximum duty cycle to approximately 95%. this allows for maximum power delivery. at very light loads, the opposite occurs, and the lt3751 reduces the peak primary current to approximately one tenth its maximum value while modulating the duty cycle below 10%. the lt3751 controls moderate loads with a combination of peak current mode control and duty cycle control.
lt3751 13 3751fc opera t ion figure 5. modes of operation (steady state) figure 6. regulation technique 3751 f05 26khz one-shot clk 26khz one-shot clk 26khz one-shot clk 26khz one-shot clk switch enable i pri switch enable i pri 110% v out, nom 105% v out, nom v out 1/10th i pk i pri maximum peak current no blanking peak current control forced blanking t per 38s charge mode heavy load operation no-load operation ... ... ... ... ... ... t t t switch enable i pri t per 38s duty cycle control duty cycle control forced blanking light load operation ... ... ... ... ... ... t 3751 f06 light load charge mode moderate load heavy load i lim ( ) duty cycle ( ) i max 1/10 i max 95% 10% load current no-load operation 0
lt3751 14 3751fc o pera t ion periodic refresh when the lt3751 enters regulation, the internal circuitry deactivates switching when the internal one-shot clock is high. the clock operates at a 1/20 th duty cycle with a minimum blank time of 1.5 s. this reset pulse is timed to drastically reduce switching frequency content within the audio spectrum and is active during all loading conditions. each reset pulse guarantees at least one energy cycle. a minimum load is required to prevent the lt3751 from entering no-load operation. heavy load operation the lt3751 enters peak current mode control at higher output load conditions. the control loop maximizes the number of switch cycles between each reset pulse. since the control scheme operates in boundary mode, the reso- nant boundary-mode period changes with varying peak primary current: period = i pk ? l pri ? 1 v trans + n v out ? ? ? ? ? ? and the power output is proportional to the peak primary current: p out = 1/ 2 ? i pk 1 v trans + n v out ? ? ? ? ? ? noise becomes an issue at very low load currents. the lt3751 remedies this problem by setting the lower peak current limit to one tenth the maximum level and begins to employ duty-cycle control. light load operation the lt3751 uses duty cycle control to drastically reduce audible noise in both the transformer ( mechanical) and the ceramic capacitors ( piezoelectric effects). internal control circuitry forces a one-shot condition at a periodic rate greater than 20 khz and out of the audio spectrum. the regulation loop then determines the number of pulses that are required to maintain the correct output voltage. figure 5 shows the use of duty-cycle control. no-load operation the lt3751 can remain in low noise regulation at very low loading conditions. below a certain load current threshold (light load operation), the output voltage would continue to increase and a runaway condition could occur. this is due to the periodic one-shot forced by the periodic refresh circuitry. by design, the lt3751 has built-in overvoltage protection associated with the fb pin. when the fb pin voltage exceeds 1.34v (20 mv), the lt3751 enters no-load operation. no-load operation does not reset with the one-shot clock. instead, the pulse train is completely load-dependent. these bursts are asynchro- nous and can contain long periods of inactivity. this allows regulation at a no-load condition but with the increase of audible noise and voltage ripple. note that when operating with no-load, the output voltage will increase 10% above the nominal output voltage.
lt3751 15 3751fc a pplica t ions i n f or m a t ion the lt3751 charger controller can be optimized for either capacitor charging only or low noise regulation applica- tions. several equations are provided to aid in the design process. safety warning large capacitors charged to high voltage can deliver a lethal amount of energy if handled improperly. it is particularly important to observe appropriate safety measures when designing the lt3751 into applications. first, create a discharge circuit that allows the designer to safely dis- charge the output capacitor. second, adequately space high voltage nodes from adjacent traces to satisfy printed circuit board voltage breakdown requirements. selecting operating mode tie the fb pin to gnd to operate the lt3751 as a capacitor charger. in this mode, the lt3751 charges the output at peak primary current in boundary mode operation. this constitutes maximum power delivery and yields the fast- est charge times. power delivery is halted once the output reaches the desired output voltage set by the rv out and rbg pins. tie a resistor divider from the fb pin to v out and gnd to operate the lt3751 as a low noise voltage regulator (refer to low noise regulation section for proper design procedures). the lt3751 operates as a voltage regulator using both peak current and duty cycle modulation to vary output current during different loading conditions. selecting component parameters most designs start with the initial selection of v trans , v out , c out , and either charge time, t charge , (capacitor charger) or p out,max ( regulator). these design inputs are then used to select the transformer ratio, n, the peak primary current, i pk , and the primary inductance, l pri . figure 7 can be used as a rough guide for maximum power output for a given v trans and i pk . selecting transformer turns ratio the transformer ratio, n, should be selected based on the input and output voltages. smaller n values equate to faster charge times and larger available output power. note that drastically reducing n below the v out /v trans ratio will increase the flyback voltage on the drain of the nmos and increase the current through the output diode. the ratio, n, should not be drastically increased either, due to the increased capacitance, n 2 ? c sec , reflected to the primary. a good choice is to select n equal to v out /v trans . n v out v trans choosing capacitor charger i pk when operating the lt3751 as capacitor charger, choose i pk based on the required capacitor charge time, t charge , and the initial design inputs. i pk = 2 ? n ? v trans + v out ( ) ? c out ? v out efficiency ? v trans ? t charge ? t d ( ) the converter efficiency varies over the output voltage range. the i pk equation is based on the average effi- ciency over the entire charging period. several factors can cause the charge time to increase. efficiency is the most dominant factor and is mainly affected by the transformer winding resistance, core losses, leakage inductance, and transistor r ds . most applications have overall efficiencies above 70%. figure 7. maximum power output peak primary current (a) v trans (v) 3751 f07 100 10 20 30 40 50 60 70 80 90 0 1 10 100 p = 20 watts p = 50 watts p = 100 watts
lt3751 16 3751fc a pplica t ions i n f or m a t ion the total propagation delay, t d , is the second most dominant factor that affects efficiency and is the summation of gate driver on-off propagation delays and the discharge time associated with the secondary winding capacitance. there are two effective methods to reduce the total propagation delay. first, reduce the total capacitance on the secondary winding, most notably the diode capacitance. second, reduce the total required nmos gate charge. figure 8 shows the effect of large secondary capacitance. the energy stored in the secondary winding capacitance is ? ? c sec ? v out 2 . this energy is reflected to the primary when the diode stops forward conduction. if the reflected capacitance is greater than the total nmos drain capaci- tance, the drain of the nmos power switch goes negative and its intrinsic body diode conducts. it takes some time for this energy to be dissipated and thus adds to the total propagation delay. choosing regulator maximum i pk the i pk parameter in regulation mode is calculated based on the desired maximum output power instead of charge time like that in a capacitor charger application. i pk = 2 ? p out(avg) efficiency ? 1 v trans + n v out ? ? ? ? ? ? note that the lt3751 regulation scheme varies the peak current based on the output load current. the maximum i pk is only reached during charge mode or during heavy load conditions where output power is maximized. figure 8. effect of secondary winding capacitance v drain 3751 f08 i sec i pri no sec. capacitance sec. discharge t transformer design the transformers primary inductance, l pri , is determined by the desired v out and previously calculated n and i pk parameters. use the following equation to select l pri : l pri = 3 s ? v out i pk ? n the previous equation guarantees that the v out comparator has enough time to sense the flyback waveform and trip the done pin latch. operating v out significantly higher than that used to calculate l pri could result in a runaway condition and overcharge the output capacitor. the l pri equation is adequate for most regulator applica- tions. note that if both i pk and n are increased significantly for a given v trans and v out , the maximum i pk will not be reached within the refresh clock period. this will result in a lower than expected maximum output power. to prevent this from occurring, maintain the condition in the follow- ing equation. l pri < 38 s i pk ? 1 v trans + n v out ? ? ? ? ? ? the upper constraint on l pri can be reduced by increas- ing v trans and starting the design process over. the best regulation occurs when operating the boundary-mode frequency above 100khz ( refer to operation section for boundary-mode definition). figure 9 defines the maximum boundary-mode switching frequency when operating at a desired output power level and is normalized to l pri /p out ( h/watt). the relation- ship of output power, boundary-mode frequency, i pk , and primary inductance can be used as a guide throughout the design process.
lt3751 17 3751fc figure 9. maximum switching frequency peak primary current (a) l pri /watt (h/watt) 3751 f09 10.000 0.010 0.100 1.000 0.001 1 10 100 f max = 50khz f max = 100khz f max = 200khz applica t ions in f or m a t ion table 1. recommended transformers manufacturer part number size l w h (mm) maximum i pri (a) l pri (h) turns ratio ( pri: sec) coilcraft www.coilcraft.com da2033-al da2034-al ga3459-bl ga3460-bl ha4060-al ha3994-al 17.4 24.1 10.2 20.6 30 11.3 32.65 26.75 14 32.65 26.75 14 34.29 26.75 14 34.29 28.75 14 5 10 20 50 2 5 10 10 5 2.5 300 7.5 1:10 1:10 1:10 1:10 1:3 2:1:3:3* wrth elektronik/midcom www.we-online.com 750032051 750032052 750310349 750310355 28.7 22 11.4 28.7 22 11.4 36.5 42 23 36.5 42 23 5 10 20 50 10 10 5 2.5 1:10 1:10 1:10 1:10 sumida www.sumida.com c8117 c8119 ps07-299 ps07-300 23 18.6 10.8 32.2 27 14 32.5 26.5 13.5 32.5 26.5 13.5 5 10 20 50 10 10 5 2.5 1:10 1:10 1:10 1:10 tdk www.tdk.com dct15efd-u44s003 dct20efd-u32s003 dct25efd-u27s005 22.5 16.5 8.5 30 22 12 27.5 33 15.5 5 10 20 10 10 5 1:10 1:10 1:10 *transformer has three secondaries where the ratio is designated as pri:sec1:sec2:sec3 rv trans , rv out and r dcm selection rv trans sets the common-mode reference voltage for both the dcm comparator and v out comparator. select rv trans from table 2 based on the transformer supply voltage range, v trans , and the maximum trip voltage, v drain (v drain -v trans ). the rv trans pin is connected to an internal 40 a current source. pin current increases as the pin voltage is taken higher than the internal 60 v zener clamp. the lt3751 can operate from v trans greater than the 60 v internal zener clamps by limiting the rv trans pin current to 250a. operating v trans above 200 v requires the use of resis- tor dividers. tw o applications are presented that operate table 2. suggested rv trans , rv out , and r dcm values v trans range (v) ?v drain range (v) rv trans (k) rv out (k) r dcm (k) 4.75 to 55 0 to 5 5.11 5.11 2.32 4.75 to 60 2.5 to 50 25.5 25.5 11.5 5 to 80 40.2 40.2 18.2 8 to 80 8 to 160 80.6 80.6 36.5 80 to 200 2ma ? rv out v trans ? 55v 0.25 v trans ? 55v 0.25 0.86 ? rv trans >200 resistor divider dependent use resistor divider use resistor divider use resistor divider
lt3751 18 3751fc a pplica t ions i n f or m a t ion with v trans between 100 v and 400v ( refer to typical applications section). consult applications engineering for applications with v trans operating above 400v. rv out is required for capacitor charger applications but may be removed for regulator applications. note that the v out comparator can be used as secondary protection for regulator applications. if the v out comparator is used for protection, design v out,trip 15% to 20% higher than the regulation voltage. tie the rv out pin to ground when rv out resistor is removed. r dcm needs to be properly sized in relation to rv trans . improper selection of r dcm can lead to undesired switching operation at low output voltages. use table 2 to size r dcm . parasitic capacitance on rv trans , rv out , and r dcm should be minimized. capacitances on these nodes slow down the response times of the v out and dcm comparators . keep the distance between the resistor and pin short. it is recommended to remove all ground and power planes underneath these pins and their respective components (refer to the recommended board layout at the end of this section). r bg selection r bg sets the trip current (0.98/r bg ) and is directly related to the selection of rv out . the best accuracy is achieved with a trip current between 100 a and 2 ma. choosing rv out from table 2 meets this criterion. use the following table 3. recommended nmos transistors manufacturer part number i d (a) v ds(max) (v) r ds(on) (m) q g(tot) (nc) package fairchild semiconductor www.fairchildsemi.com fds2582 fqb19n20l fqp34n20l fqd12n20l fqb4n80 4.1 21 31 12 3.9 150 200 200 200 800 66 140 75 280 3600 11 27 55 16 19 so-8 d 2 pak to-220 dpak d 2 pak on semiconductor www.onsemi.com mtd6n15t4g ntd12n10t4g ntb30n20t4g ntb52n10t4g 6 12 30 52 150 100 200 100 300 165 81 30 15 14 75 72 dpak dpak d 2 pak d 2 pak vishay www.vishay.com si7820dn si7818dn sup33n20-60p 2.6 3.4 33 200 150 200 240 135 60 12.1 20 53 1212-8 1212-8 to-220 equation to size r bg (v trans 80v): r bg = 0.98 ? n ? rv out v out,trip + v diode ? ? ? ? ? ? tie r bg pin to ground when not using the v out compara- tor. consult applications engineering for calculating r bg when operating v trans above 80v. nmos switch selection choose an external nmos power switch with minimal gate charge and on-resistance that satisfies current limit and voltage break-down requirements. the gate is nominally driven to v cc C 2 v during each charge cycle. ensure that this does not exceed the maximum gate to source voltage rating of the nmos but enhances the channel enough to minimize the on-resistance. similarly, the maximum drain-source voltage rating of the nmos must exceed v trans + v out /n or the magnitude of the leakage inductance spike, whichever is greater. the maximum instantaneous drain current rating must exceed selected current limit. because the switching period de- creases with output voltage, the average current though the nmos is greatest when the output is nearly charged and is given by: i avg,m = i pk ? v out(pk) 2(v out(pk) + n ? v trans ) see table 3 for recommended external nmos transistors.
lt3751 19 3751fc applica t ions in f or m a t ion gate driver operation the lt3751 gate driver has an internal, selectable 10.5v or 5.6 v clamp with up to 2 a current capability (using lvgate). for 10.5 v operation, tie clamp pin to ground, and for 5.6 v operation, tie the clamp pin to the v cc pin. choose a clamp voltage that does not exceed the nmos manufacturers maximum v gs ratings. the 5.6 v clamp can also be used to reduce lt3751 power dissipation and increase efficiency when using logic-level fets. the typical gate driver overshoot voltage is 0.5 v above the clamp voltage. the lt3751s gate driver also incorporates a pmos pull- up device via the lvgate pin. the pmos pull-up driver should only be used for v cc applications of 8 v or below. operating lvgate with v cc above 8 v will cause perma- nent damage to the part. lvgate is active when tied to hvgate and allows rail-to-rail gate driver operation. this is especially useful for low v cc applications, allowing bet- ter nmos drive capability. it also provides the fastest rise times, given the larger 2 a current capability verses 1.5a when using only hvgate. output diode selection the output diode(s) are selected based on the maximum repetitive reverse voltage (v rrm ) and the average forward current (i f(av ) ). the output diodes v rrm should exceed v out + n ? v trans . the output diodes i f(av ) should exceed i pk /2n , the average short- circuit current. the average diode current is also a function of the output voltage. table 4. recommended output diodes manufacturer part number i f(av ) (a) v rrm (v) t rr (ns) package central semiconductor www.centralsemi.com cmr1u-10m cmsh2-60m cmsh5-40 1 2 5 1000 60 40 100 sma sma smc fairchild semiconductor www.fairchildsemi.com es3j es1g es1j 3 1 1 600 400 600 35 35 35 smc sma sma on semiconductor www.onsemi.com murs360 mura260 mura160 3 2 1 600 600 600 75 75 75 smc sma sma vishay www.vishay.com usb260 us1g us1m gurb5h60 2 1 1 5 600 400 1000 600 30 50 75 30 smb sma sma d 2 pak i avg = i pk ? v trans 2 ? (v out + n ? v trans ) the highest average diode current occurs at low output voltages and decreases as the output voltage increases. reverse recovery time, reverse bias leakage and junction capacitance should also be considered. all affect the over - all charging efficiency. excessive diode reverse recovery times can cause appreciable discharging of the output capacitor, thereby increasing charge time. choose a diode with a reverse recovery time of less than 100 ns. diode leakage current under high reverse bias bleeds the output capacitor of charge and increases charge time. choose a diode that has minimal reverse bias leakage current. diode junction capacitance is reflected back to the primary, and energy is lost during the nmos intrinsic diode conduction. choose a diode with minimal junction capacitance. table 4 recommends several output diodes for various output voltages that have adequate reverse recovery times. setting current limit placing a sense resistor from the positive sense pin, csp, to the negative sense pin, csn, sets the maximum peak switch current. the maximum current limit is nominally 106mv/r sense . the power rating of the current sense resistor must exceed: p rsense i 2 pk ? r sense 3 v out(pk) v out(pk) + n ? v trans ? ? ? ? ? ? additionally, there is approximately a 180 ns propaga- tion delay from the time that peak current limit is
lt3751 20 3751fc a pplica t ions i n f or m a t ion detected to when the gate transitions to the low state. this delay increases the peak current limit by (v trans ) (180ns)/l pri . sense resistor inductance ( l rsense ) is another source of current limit error. l rsense creates an input offset voltage (v os ) to the current comparator and causes the current comparator to trip early. v os can be calculated as: v os = v trans ? l rsense l primary ? ? ? ? ? ? the change in current limit becomes v os /r sense . the error is more significant for applications using large di/dt ratios in the transformer primary. it is recommended to use very low inductance (< 2 nh) sense resistors. several resistors can be placed in parallel to help reduce the inductance. care should also be taken in placement of the sense lines. the negative return line, csn, must be a dedicated trace to the low side resistor terminal. haphazardly routing the csn connection to the ground plane can cause inaccurate current limit and can also cause an undesirable discontinu- ous charging profile. done and fault pin design both the done and fault pins require proper pull-up resistors or current sources. limit pin current to 1ma into either of these pins . 100 k? pull-up resistors are recommended for most applications. both the done and fault pins are latched in the low output state. resetting either latch requires the charge pin to be toggled. a fault condition will also cause the done pin to go low. a third, non-latching condition occurs during startup when the charge pin is driven high. during this start-up condition, both the done and fault pins will go low for several micro seconds. this indicates the internal rails are still ramping to their proper levels. external rc filters may be added to both indication pins to remove start-up indication. time constants for the rc filter should be between 5 s to 20s. under/overvoltage lockout the lt3751 provides user- programmable under and overvoltage lockouts for both v cc and v trans . use the equations in the pin functions section for proper selection of resistor values. when under/overvoltage lockout com- parators are tripped, the master latch is disabled, power delivery is halted, and the fault pin goes low. adequate supply bulk capacitors should be used to reduce power supply voltage ripple that could cause false tripping during normal switching operation. additional filtering may be required due to the high input impedance of the under/overvoltage lockout pins to prevent false tripping. individual capacitors ranging from 100 pf to 1 nf may be placed between each of the uvlo1, uvlo2, ovlo1 and ovlo2 pins and ground. disable the undervoltage lockouts by directly connecting the uvlo1 and uvlo2 pins to vcc. disable the overvoltage lockouts by directly connecting the ovlo1 and ovlo2 pins to ground. the lt3751 provides internal zener clamping diodes to protect itself in shutdown when v trans is operated above 55v. supply voltages should only be applied to uvlo1, uvlo2, ovlo1 and ovlo2 with series resistance such that the absolute maximum pin currents are not exceeded . pin current can be calculated using: i pin = v applied ? 55v r series note that in shutdown, rv trans , rv out , r dcm , uvlo1, uvlo2, ovlo1 and ovlo2 currents increase significantly when operating v trans above the zener clamp voltages and are inversely proportional to the external series pin resistances. nmos snubber design the transformer leakage inductance causes a parasitic voltage spike on the drain of the power nmos switch dur- ing the turn-off transition. transformer leakage inductance effects become more apparent at high peak primary cur- rents. the worst-case magnitude of the voltage spike is determined by the energy stored in the leakage inductance and the total capacitance on the v drain node. v d,leak = l leak ? i 2 pk c vdrain tw o problems can arise from large v d,leak . first, the magnitude of the spike may require an nmos with an
lt3751 21 3751fc figure 11. effects of rc snubber figure 10. rc snubber circuit applica t ions in f or m a t ion unnecessarily high v (br)dss which equates to a larger r ds(on) . secondly, the v drain node will ringpossibly below groundcausing false tripping of the dcm com- parator or damage to the nmos switch ( see figure 11). both issues can be remedied using a snubber. if leakage inductance causes issues, it is recommended to use a rc snubber in parallel with the primary winding, as shown in figure 10. size c snub and r snub based on the desired leakage spike voltage, known leakage inductance, and an rc time constant less than 1 s. otherwise, the leakage voltage spike can cause false tripping of the v out com- parator and stop charging prematurely. figure 11 shows the effect of the rc snubber resulting in a lower voltage spike and faster settling time. 3751 f11 l pri r snub c snub l leak ? ? c vdrain 0v 0v 3751 f12 v drain (with snubber) v drain (without snubber) i pri nmos diode conducts low noise regulation the lt3751 has the option to provide a low noise regu- lated output voltage when using a resistive voltage divider from the output node to the fb pin. refer to the selecting component parameters section to design the transformer, nmos power switch, output diode, and sense resistor. use the following equations to select the feedback resis- tor values based on the power dissipation and desired output voltage: r fbh = v out ? 1.22 ( ) 2 p d ; top feedback resistor r fbl = 1.22 v out ? 1.22 ? ? ? ? ? ? ? r fbh ; bottom feedback resistor r fbh , depending on output voltage and type used, may require several smaller values placed in series. this will reduce the risk of arcing and damage to the feedback resis- tors. consult the manufacturer s rated voltage specification for safe operation of the feedback resistors. the lt3751 has a minimum periodic refresh frequency limit of 23 khz. this drastically reduces switching frequency components in the audio spectrum. the lt3751 can oper- ate with no-load, but the regulation scheme switches to no-load operation and audible noise and output voltage ripple increase. this can be avoided by operating with a minimum load current. minimum load current periodic refresh circuitry requires an average minimum load current to avoid entering no-load operation. usually, the feedback resistors should be adequate to provide this minimum load current. i load(min) l pri ? i 2 pk ? 23khz 100 ? v out i pk is the peak primary current at maximum power delivery . the lt3751 will enter no-load operation if the minimum load current is not met. no-load operation will prevent the application from entering a runaway condition; however, the output voltage will increase 10% over the nominal regulated voltage.
lt3751 22 3751fc a pplica t ions i n f or m a t ion large signal stability large signal stability can be an issue when audible noise is a concern. figure 12 shows that the problem originates from the one-shot clock and the output voltage ripple. the load must be constrained such that the output voltage ripple does not exceed the regulation range of the error amplifier within one clock period (approximately 6mv referred to the fb pin). the output capacitance should be increased if oscillations occur or audible noise is present. use figure 13 to deter- mine the maximum load for a given output capacitance to maintain low audible noise operation. a small capacitor can also be added from the fb pin to ground to lower the ripple injected into fb pin. small signal stability the lt3751s error amplifier is internally compensated to increase its operating range but requires the converters output node to be the dominant pole. small signal stability constraints become more prevalent during heavy load- ing conditions where the dominant output pole moves to higher frequency and closer to the internal feedback poles and zeros. the feedback loop requires the output pole frequency to remain below 200 hz to guarantee small signal stability. this allows smaller r load values than the large signal constraint. thus, small signal issues should not arise if the large signal constraint is met. board layout the high voltage operation of the lt3751 demands care- ful attention to the board layout, observing the following points: 1. minimize the area of the high voltage end of the second- ary winding. 2. provide sufficient spacing for all high voltage nodes (nmos drain, v out and secondary winding of the transformer) in order to meet the breakdown voltage requirements. 3. keep the electrical path formed by c vtrans , the primary of t1, and the drain of the nmos as short as possible. increasing the length of this path effectively increases the leakage inductance of t1, potentially resulting in an overvoltage condition on the drain of the nmos. 4. reduce the total node capacitance on the rv out and r dcm pins by removing any ground or power planes underneath the r dcm and r vout pads and traces. parasitic capacitance can cause unwanted behavior on these pins. 5. thermal vias should be added underneath the exposed pad, pin 21, to enhance the lt3751s thermal perfor- mance. these vias should go directly to a large area of ground plane. 6. isolated applications require galvanic separation of the output- side ground and primary - side ground. adequate spacing between both ground planes is needed to meet voltage safety requirements. figure 13. c out(min) vs output power output power (w) 0 c out, min (f) 30 25 15 5 20 10 0 150 3751 f14 200 50 100 v out = 150v v out = 300v v out = 600v figure 12. voltage ripple stability constraint v out 3751 f13 26khz one-shot clk i pri load droop
lt3751 23 3751fc applica t ions in f or m a t ion 1 2 3 4 5 6 3751 f15 16 15 14 13 12 11 lt3751 v cc v trans power gnd charge analog gnd r uvlo2 analog gnd vias 7 8 9 10 20 19 18 17 r ovlo2 r fault r done r uvlo1 r ovlo1 r vtrans r dcm r bg r vout analog gnd v cc c vcc analog gnd single point gnd c fb r fbl r fbh3 power gnd return r sense c vtrans1 + c vtrans2 c vtrans3 + c vtrans4 power gnd return ? ? secondary primary t1 1:n c vout1 c vout2 d vout + power gnd v out r fbh2 r fbh1 m1 remove copper from all sub-layers (see item 4) figure 14. qfn package recommended board layout (not to scale)
lt3751 24 3751fc figure 15. tssop package recommended board layout (not to scale) 3751 f16 lt3751 v cc v trans power gnd charge r vtrans r uvlo1 r ovlo1 r uvlo2 r ovlo2 r fault r done r sense r dcm r bg r vout analog gnd analog gnd v cc c vcc analog gnd c fb r fbl power gnd return c vtrans1 c vtrans2 c vtrans3 + c vout2 + + c vtrans4 power gnd return ? ? secondary primary t1 1:n c vout1 d vout v out r fbh2 r fbh1 m1 remove copper from all sub-layers (see item 4) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 applica t ions in f or m a t ion
lt3751 25 3751fc typical a pplica t ions 42a capacitor charger charge clamp v cc done fault uvlo1 ovlo1 uvlo2 ovlo2 rdcm rv out hvgate lvgate csp csn fb rv trans t1** 1:10 d1 v out 500v v trans 12v to 24v v cc 3751 ta02 lt3751 gnd rbg r6 40.2k off on c3 1000f c2 10f 3 v cc 12v to 24v c1 10f ? ? r7, 18.2k r8, 40.2k m1, m2* r5 2.5m d2*** + + c4 1200f r9 787 v trans v cc r10, 100k r11, 100k r1, 191k r2, 475k r3, 191k r4, 475k c1: 25v x5r or x7r ceramic capacitor c2: 25v x5r or x7r ceramic capacitor c3: 25v electrolytic c4: hitachi fx22l122y 1200f, 550v electrolytic or: cornell dubilier dcmc192t550ce2b 1900f, 550v electrolytic d1, d2: vishay gurb5h60 600v, 5a ultrafast rectifier m1, m2: 2 parallel vishay sup33n20-60p 200v, 33a nmos r1 thru r4, r6 thru r11: use 1% 0805 resistors r5: use 2 parallel 5m irc lr series 2512 resistors t1: coilcraft ga3460-bl 50a surace mount transformer danger high voltage! operation by high voltage trained personnel only for any v out voltage between 50v and 500v select r9 according to: 4.7nf y-rated * m1, m2 requires proper heatsink/thermal dissipation to meet manufacturer?s specifications ** thermal dissipation of t1 will limit the charge/discharge duty cycle of c4 *** d2 may be omitted for output voltage operation below 300v efficiency output capacitor charge times charging waveform output voltage (v) 50 efficiency (%) 85 80 75 70 65 450 3751 ta02b 250 350 150 v trans = 12v v trans = 24v output capacitance (f) 200 charge time (ms) 1200 800 400 0 1000 3751 ta02c 1200 800 600 400 v out = 500v, v trans = 24v v out = 500v, v trans = 12v v out = 300v, v trans = 24v v out = 300v, v trans = 12v v out = 100v, v trans = 24v v out = 100v, v trans = 12v 100ms/div 3751 ta02d v out = 500v v trans = 24v c4 = 1200f average input current 5a/div v out 100v/div r9 = 0.98 t n t 40.2k ? v out + v diode ? ? ? ? ? ?
lt3751 26 3751fc t ypical applica t ions efficiency (v out = 500v) load regulation (v out = 500v) steady-state operation with 100ma load current high voltage regulator charge clamp v cc done fault uvlo1 ovlo1 uvlo2 ovlo2 rdcm rv out hvgate lvgate csp csn fb rv trans t1* 1:10 d1 v out 100v to 500v v trans 5v to 24v v cc 3751 ta04 lt3751 gnd rbg r6 40.2k off on c3 680f c2 5 2.2f c1 10f ? ? r7, 18.2k r8, 40.2k m1* r5 6m + + c4*** 100f r9 v trans v cc r2, 475k r1, 69.8k r4, 475k r3, 69.8k c1: 25v x5r or x7r ceramic c2: 25v x5r or x7r ceramic c3: 25v electrolytic c5: tdk ckg57nx7r2j474m d1: vishay us1m 1000v m1: fairchild fqp34n20l r1 thru r4, r6 thru r9, r11: use 1% 0805 r5: irc lr series 2512 resistors r10: use 200v 1206 resistor(s) t1: coilcraft ga3459-al to micro v cc 5v to 24v c5 0.47f r11 r10** danger high voltage! operation by high voltage trained personnel only c6 10nf * m1 and t1 require proper heatsink/thermal dissipation to meet manufacturer?s specifications ** depending on desired output voltages, r10 must be split into multiple resistors, to meet manufacturer?s voltage specification. *** c4 must be sized to meet large signal stability criteria described in the applications information section 10s/div 3751 ta03b v drain 50v/div i pri 10a/div v out ac coupled 2v/div i load (ma) 0 efficiency (%) 90 85 75 80 70 65 60 200 3751 ta03c 100 150 50 v trans = 24v v trans = 12v v trans = 5v i load (ma) 0 output voltage (v) 515 510 505 500 495 200 3751 ta03d 100 150 50 v trans = 24v v trans = 12v v trans = 5v 10s/div 3751 ta03e v drain 50v/div i pri 10a/div v out coupled 2v/div steady-state operation with 1.1ma load current suggested component values v out (v) i out(max) (ma) at v trans = 5v, 5% v out deflection i out(max) (ma) at v trans = 24v, 5% v out deflection r9 (k) r11 (k) r10 (k) 100 180 270 3.32 0.383 30.9 200 110 315 1.65 0.768 124 300 75 245 1.10 1.13 274 400 55 200 0.825 1.54 499 500 ? 40 170 tie to gnd 1.74 715 ? transformer primary inductance limits v out comparator operation to v out = 400v max . rv out and r bg should be tied to ground when operating v out above 400v.
lt3751 27 3751fc v cc done fault uvlo1 ovlo1 uvlo2 ovlo2 charge clamp rdcm rv out hvgate lvgate fb csp csn rv trans t1* 1:3 d1 f1, 1a v out 50v to 500v v trans 100v to 400vdc v cc 3751 ta04a lt3751 gnd rbg r6 625k off on c3 47f c2 2.2f 5 c1 10f ? ? r8 417k r10 208k r5 20 r7, 96.2k m1** r13 68m r12 r9 67.3k r11 32.1k d2 + + c4 220f v trans v cc r2, 9m r1, 1.5m r4, 475k r3, 154k c1: 25v x5r or x7r ceramic c2: 630v x5r or x7r ceramic c3: 450v illinois cap 476cke450mqw c4: 50v to 500v electrolytic c5: tdk ckg57nx7r2j474m d1, d2: vishay us1m 1000v f1: bussmann pcb-1-r m1: fairchild fqb4n80 r1, r2: 2 x 1206 resistors in series, 1% r3 thru r5, r9, r12: 0805 resistors, 1% r6, r10: 3 x 1206 resistors in series, 0.1% r7, r11: 0805 resistors, 0.1% r8: 3 x 1206 resistors in series, 1% r13: irc lr series 1206 resistor, 1% t1: coilcraft ha4060-al * t1 requires proper thermal management to achieve desired output power levels ** m1 requires proper heat sink/thermal dissipation to meet manufacturer?s specifications for any output voltage between 50v to 500v, set r12 given by: to micro v cc 10v to 24v c5 0.47f danger high voltage! operation by high voltage trained personnel only 4.7nf y-rated input voltage (v) 100 v out,trip (v) 520 510 300 200 400 500 490 530 850 700 550 400 1000 3751 ta04b v out,trip charge time charge time (ms) output voltage (v) 50 efficiency (%) 85 90 95 80 75 250 450 150 350 70 65 100 3751 ta04c v in = 100v v in = 250v v in = 400v 100ms/div 3751 ta04d v out = 500v v trans = 300v v out = 12v average input current 200ma/div charge 10v/div v out 100v/div output trip voltage and charge time (v out = 500v, c out = 220f) efficiency charging waveform 1.6a high input voltage, isolated capacitor charger t ypical applica t ions r12 = 0.98 v out,trip 3 t r10 + 40a t 2
lt3751 28 3751fc charge clamp v cc done fault uvlo1 ovlo1 uvlo2 ovlo2 rdcm rv out hvgate lvgate csp csn fb rv trans t1* 1:3 d1 f1, 1a v out 100v to 500v v trans 100v to 400vdc v cc 3751 ta05a lt3751 gnd rbg r6, 625k off on c3 47f c2 2.2f 5 c1 10f ? ? r8, 417k r5, 20 r7, 97.6k m1** r12 68m r9 67.3k d2 + + c4 100f v trans v cc r2, 9m r1, 1.5m r4, 475k r3, 154k c1: 25v x5r or x7r ceramic c2: 630v x5r or x7r ceramic c3: 450v illinois cap 476cke450mqw c4: 50v to 500v electrolytic c5: tdk ckg57nx7r2j474m c6: 6.3v x5r or x7r ceramic d1, d2: vishay us1m 1000v f1: bussmann pcb-1-r m1: fairchild fqb4n80 r1, r2: 2 x 1206 resistors in series, 1% r3 thru r5, r7, r9, r11: 0805 resistors, 1% r6, r8: 3 x 1206 resistors in series, 1% r10: 1206 resistor(s), 1% r12: irc lr series 1206 resistor, 1% t1: coilcraft ha4060-al * t1 requires proper thermal management to achieve desired output power levels ** m1 requires proper heat sink/thermal dissipation to meet manufacturer?s specifications *** depending on desired output voltage, r10 must be split into multiple resistors to meet manufacturer?s voltage specification to micro v cc 10v to 24v c5 0.47f r11 r10*** danger high voltage! operation by high voltage trained personnel only c6 10nf output current (ma) 0 40 efficiency (%) 50 60 70 80 90 25 50 3751 ta05b 75 v in = 400v v in = 250v v in = 100v input voltage (v) 100 395 output voltage (v) 396 397 398 200 300 3751 ta05c 400 i out = 25ma i out = 50ma i out = 10ma 10s/div 3751 ta05d v in = 200v v out = 400v v drain 100v/div i pri 2a/div efficiency line regulation steady-state operation with 50ma load current t ypical applica t ions high input voltage, high output voltage regulator suggested component values v out (v) i out(max) (ma) at v trans = 100v, 1% v out deflection i out(max) (ma) at v trans = 400v, 1% v out deflection r10 (k) r11 (k) 100 55 130 30.9 0.383 200 110 150 124 0.768 300 95 175 274 1.13 400 80 130 499 1.54 500 65 140 715 1.74
lt3751 29 3751fc isolated 282v voltage regulator t ypical applica t ions done fault uvlo1 ovlo1 uvlo2 ovlo2 v cc charge clamp rdcm rv out v in gnd oc opto v cc comp fb hvgate lvgate fb csp csn rv trans t1 d5 v out 282v 225ma v trans v cc 3751 ta06a lt3751 gnd rbg r3 210k off on c3 22f 2 c1 100pf c4 1f 2 c2 1f ? ? ? r7 475 r4 105k r5 210k m2 r6 40m r18 1k r8 2.49k r17 221k r16 249k 4.7nf y rated r1 49.9k d1 d6 u2 lt4430 v trans v cc r10, 4.3m r9, 2.7m r2, 10 isolation boundary npb np ns nsb r12, 442k r11, 84.5k c1, c8: 16v cog ceramic c2: 16v x5r or x74 ceramic c3: 350v electrolytic c4: 250v x5r or x7r ceramic c5, c6, c11, c12: 630v x5r or x7r ceramic c7: 350v electrolytic c9, c10: 25v x5r or x7r ceramic f1: 250v, 2a fuse r1: 2010 resistor, 1% r2, r3, r6, r16, r17: 1206 resistors, 1% r4, r5: two 1206 resistors in series, 1% r7 thru r12, r15 thru r20: 0805 resistors, 1% d1: 12v zener d2: vishay murs140 d3: vishay p6ke200a d4: vishay murs160 d5: stmicroelectronics stth112a d6: vishay bat54 d7: nxp semiconductors bas516 m1: vishay irf830 m2: stmicroelectronics stb11nm60fd t1: tdk srw24lq (np:ns:npb:nsb = 1:2:0.08:0.08) u1: nec ps2801-1 u2: linear technology lt4430 to micro v trans 100v to 200vdc f1, 2a c5 0.01f danger high voltage! operation by high voltage trained personnel only d4 d3 m1 c9 3.3f c8 22nf r19 3.16k c10 0.47f ? r15 5.11 d7 u1 d2 r20 274 c6 0.1f + + c7 400f i out (ma) 0 ?0.50 output voltage error (v) 0 50 100 200 150 0.50 ?0.25 0.25 250 3751 ta06b 100 efficiency (%) 100 95 90 85 80 75 70 180 140 3751 ta06c 200 160 input voltage (v) 120 63w output 48w output 25w output 20s/div 3751 ta06d i primary 2a/div v drain 100v/div 20s/div 3751 ta06e i primary 2a/div v drain 100v/div load regulation efficiency steady-state operation with 225ma load current steady-state operation with 7.1ma load current
lt3751 30 3751fc ?i vout2 , i vout3 ** (ma) ?v out2 , v out3 (v) 18 16 14 20 3751 ta07b v in = 24v v in = 12v v in = 5v 1 10 100 1000 **source/sink identical currents from both v out2 and v out3 , respectively wide input voltage range, 15 watt, triple output voltage regulator t ypical applica t ions done fault uvlo1 ovlo1 uvlo2 ovlo2 v cc charge clamp rdcm rv out hvgate lvgate fb csp csn rv trans d1 t1 2:1:3:3 (p1:s1:s2:s3) v out3 +15v v in 5v to 24v v cc 3751 ta07a lt3751 gnd rbg r5 25.5k off on c4 470f c7 10f c1 10f ? ? c3 10f r12 4.99k r7 25.5k r6 11.5k m1 r11 25m r10 100 r8 2.21k r9 309 r4, 464k r3, 66.5k p1 s3 r2, 100k r1, 100k c1, c3: 25v x5r or x7r ceramic c2: 25v sanyo 25me1000ax c4, c5: 35v sanyo 35me470ax c6: 10v kemet t520d107m010ase055 c7, c8: 16v ceramic, tdk c4532x7r1e106m c9: 6.3v ceramic, tdk c4532x5r0j107m d1, d2: central semi cmsh2-60m d3: central sem1 cmsh5-40 m1: fairchild fqd12n20l r1 thru r10, r12, r13: 0805 resistor, 1% r11: 1206 resistor, 1% t1: coilcraft ha3994-al, 2:1:3:3 (p1:s1:s2:s3) d2 v out2 ?15v c5 470f c8 10f ? r13 4.99k s2 d3 v out1 +5v c6 100f 2 c9 100f ? s1 + + + c2 1000f 2 + ?i vout2 , i vout3 ** (ma) ?v out2 , v out3 (v) 22 24 20 18 16 14 26 3751 ta07c v in = 24v v in = 12v v in = 5v 1 10 100 1000 ?i vout2 + i vout3 (ma) 0 efficiency (%) 80 85 75 70 400 200 600 800 65 60 90 3751 ta07d v in = 24v v in = 12v v in = 5v cross regulation (i vout1 = 100ma) efficiency (i vout1 = 500ma) maximum output conditions v cc (v) p out(max) (w) i out(max) * (ma) v out1 v out2 v out3 5 6.5 750 300 300 12 10 1750 300 300 24 13 2500 300 300 *all other output currents set to 0ma cross regulation (i vout1 = 500ma)
lt3751 31 3751fc fe20 (cb) tssop rev i 0211 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 111214 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev i) exposed pad variation cb p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
lt3751 32 3751fc ufd package 20-pin plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1711 rev b) p ackage descrip t ion 4.00 0.10 (2 sides) 1.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 19 20 1 2 bottom view?exposed pad 2.50 ref 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.20 or c = 0.35 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd20) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 2.65 0.05 2.50 ref 4.10 0.05 5.50 0.05 1.50 ref 3.10 0.05 4.50 0.05 package outline r = 0.05 typ 2.65 0.10 3.65 0.10 3.65 0.05 0.50 bsc please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
lt3751 33 3751fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number b 5/10 updated fault (pin 6/pin 4) description in pin functions 7 updated done (pin 7/pin 5) description in pin functions 8 updated block diagram 9 revised applications information section 17, 18 revised typical applications illustration 30 c 6/12 revised applications information section 20 corrected schematic r8 value from 3.40k to 2.21k 30 updated fe package drawing 31 (revision history begins at rev b)
lt3751 34 3751fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0612 rev c ? printed in usa r ela t e d p ar t s typical a pplica t ion 300v regulated power supply part number description comments ltc3225 150ma supercapacitor charger v in : 2.75v to 5.5v, charges two supercapacitors in series to 4.8v or 5.3v lt3420/lt3420-1 1.4a/1a, photoflash capacitor charger with automatic top -off charges 220f to 320v in 3.7 seconds from 5v, v in : 2.2v to 16v, i sd < 1a, 10-lead ms package lt3468/lt3468-1/ lt3468-2 1.4a, 1a, 0.7a, photoflash capacitor charger v in : 2.5v to 16v, charge time: 4.6 seconds for lt3468 (0v to 320v, 100f, v in = 3.6v), i sd < 1a, thinsot? package lt3484-0/lt3484-1/ lt3484-2 1.4a, 0.7a, 1a photoflash capacitor charger v in : 1.8v to 16v, charge time: 4.6 seconds for lt3484-0 (0v to 320v, 100f, v in = 3.6v), i sd < 1a, 2mm 3mm 6-lead dfn package lt3485-0/lt3485-1/ lt3485-2/lt3485-3 1.4a, 0.7a, 1a, 2a photoflash capacitor charger with output voltage monitor and integrated igbt v in : 1.8v to 10v, charge time: 3.7 seconds for lt3485-0 (0v to 320v, 100f, v in = 3.6v), i sd < 1a, 3mm 3mm 10-lead dfn package lt3585-0/lt3585-1/ lt3585-2/lt3585-3 1.2a, 0.55a, 0.85a, 1.7a photoflash capacitor charger with adjustable input current and igbt drivers v in : 1.5v to 16v, charge time: 3.3 seconds for lt3585-3 (0v to 320v, 100f, v in = 3.6v), i sd < 1a, 3mm 2mm dfn-10 package lt3750 capacitor charger controller v in : 3v to 24v, charge time: 300ms for (0v to 300v, 100f) msop-10 package uvlo1 ovlo1 uvlo2 ovlo2 rdcm rv trans t1 1:10 d1 v out 300v 0ma to 270ma v trans 24v v cc c3 680f 3751 ta08 lt3751 gnd rbg r6 40.2k off on c2 2.2f 5 v cc 24v c1 10f ? ? r7 18.2k m1 r5 6m + + c4 20f r8* 274k * depending on desired output voltage, r8 must be split into multiple resistors to meet manufacturer?s voltage specification. v trans v cc r9 1.13k r1 432k r2 475k r4 475k r3 432k to micro c1: 25v x5r or x7r ceramic capacitor c2: 25v x5r or x7r ceramic capacitor c3: 25v electrolytic c4: 330v rubycon photoflash capacitor d1: vishay us1m 1000v m1: fairchild fqp34n20l r1 through r4: use 1% 0805 resistors r5: irc lr series 2512 resistor t1: sumida ps07-299, 20a transformer csn fb done fault v cc clamp charge rv out hvgate lvgate csp c5 10nf

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